diff --git a/volatility3/framework/layers/intel.py b/volatility3/framework/layers/intel.py
index 296ea36ca..94b15d3a0 100644
--- a/volatility3/framework/layers/intel.py
+++ b/volatility3/framework/layers/intel.py
@@ -329,6 +329,10 @@ class WindowsIntelPAE(WindowsMixin, IntelPAE):
 
 class WindowsIntel32e(WindowsMixin, Intel32e):
 
+    # TODO: Fix appropriately in a future release.
+    # Currently just a temprorary workaround to deal with custom bit flag
+    # in the PFN field for pages in transition state.
+    # See https://github.com/volatilityfoundation/volatility3/pull/475
     _maxphyaddr = 45
     
     def _translate(self, offset: int) -> Tuple[int, int, str]: