diff --git a/volatility/framework/contexts/__init__.py b/volatility/framework/contexts/__init__.py
index a911ebeca..7ea40fbe0 100644
--- a/volatility/framework/contexts/__init__.py
+++ b/volatility/framework/contexts/__init__.py
@@ -73,7 +73,7 @@ class Context(interfaces.context.ContextInterface):
         """A Memory object, allowing access to all data and translation layers currently available within the context"""
         return self._memory
 
-    # ## Address Space Functions
+    # ## Translation Layer Functions
 
     def add_layer(self, layer: interfaces.layers.DataLayerInterface) -> None:
         """Adds a named translation layer to the context
diff --git a/volatility/framework/layers/intel.py b/volatility/framework/layers/intel.py
index 40436a581..45e45e273 100644
--- a/volatility/framework/layers/intel.py
+++ b/volatility/framework/layers/intel.py
@@ -76,9 +76,9 @@ class Intel(interfaces.layers.TranslationLayerInterface):
 
     @classproperty
     def page_size(cls) -> int:
-        """Page size for the intel address space.
+        """Page size for the intel memory layers
 
-        All Intel address spaces work on 4096 byte pages"""
+        All Intel layers work on 4096 byte pages"""
         return 1 << cls._page_size_in_bits
 
     @classproperty
diff --git a/volatility/framework/layers/lime.py b/volatility/framework/layers/lime.py
index f9ffcc969..422d9a9c6 100644
--- a/volatility/framework/layers/lime.py
+++ b/volatility/framework/layers/lime.py
@@ -32,7 +32,7 @@ class LimeFormatException(exceptions.LayerException):
 class LimeLayer(segmented.SegmentedLayer):
     """A Lime format TranslationLayer. Lime is generally used to store
     physical memory images where there are large holes in the physical
-    address space"""
+    layer"""
 
     priority = 21
 
diff --git a/volatility/framework/layers/registry.py b/volatility/framework/layers/registry.py
index 93f125f3a..766bf350a 100644
--- a/volatility/framework/layers/registry.py
+++ b/volatility/framework/layers/registry.py
@@ -75,7 +75,7 @@ class RegistryHive(interfaces.layers.TranslationLayerInterface):
         self._base_block = self.hive.BaseBlock.dereference()
 
         self._minaddr = 0
-        # If there's no base_block, we don't know how big the address space is
+        # If there's no base_block, we don't know how big the hive layer is
         # We also don't know the root_cell_offset, so we use a hardcoded value of 0x20
         self._maxaddr = self._base_block.Length or 0x7fffffff
 
diff --git a/volatility/framework/objects/__init__.py b/volatility/framework/objects/__init__.py
index 89549b625..ab10ddc45 100644
--- a/volatility/framework/objects/__init__.py
+++ b/volatility/framework/objects/__init__.py
@@ -277,7 +277,7 @@ class Pointer(Integer):
     @classmethod
     def _unmarshall(cls, context: interfaces.context.ContextInterface, data_format: DataFormatInfo,
                     object_info: ObjectInformation) -> Any:
-        """Ensure that pointer values always fall within the address space of the layer they're constructed on
+        """Ensure that pointer values always fall within the domain of the layer they're constructed on
 
            If there's a need for all the data within the address, the pointer should be recast.  The "pointer"
            must always live within the space (even if the data provided is invalid).