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https://github.com/volatilityfoundation/volatility3.git
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Layers: Don't map intel out-of-bounds addresses
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@@ -52,6 +52,7 @@ class Intel(linear.LinearlyMappedLayer):
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self._index_shift = int(math.ceil(math.log2(struct.calcsize(self._entry_format))))
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@classproperty
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@functools.lru_cache()
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def page_size(cls) -> int:
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"""Page size for the intel memory layers.
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@@ -60,16 +61,19 @@ class Intel(linear.LinearlyMappedLayer):
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return 1 << cls._page_size_in_bits
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@classproperty
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@functools.lru_cache()
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def bits_per_register(cls) -> int:
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"""Returns the bits_per_register to determine the range of an
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IntelTranslationLayer."""
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return cls._bits_per_register
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@classproperty
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@functools.lru_cache()
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def minimum_address(cls) -> int:
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return 0
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@classproperty
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@functools.lru_cache()
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def maximum_address(cls) -> int:
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return (1 << cls._maxvirtaddr) - 1
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@@ -119,6 +123,10 @@ class Intel(linear.LinearlyMappedLayer):
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position = self._initial_position
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entry = self._initial_entry
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if self.minimum_address > offset > self.maximum_address:
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raise exceptions.PagedInvalidAddressException(self.name, offset, position + 1, entry,
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"Entry outside virtual address range: " + hex(entry))
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# Run through the offset in various chunks
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for (name, size, large_page) in self._structure:
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# Check we're valid
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